--
-- CSSE2000 8 Bit Microprocessor
-- Copyright (C) 2011 Nathan Rossi (University of Queensland)
--
-- THIS DESIGN/CODE IS PROVIDED TO YOU UNDER THE FOLLOWING LICENSE:
--
-- All material is restricted to use in the CSSE2000 Project for 2011.
-- You may not redistribute the file/code/design, without the consent of the author.
--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library work;
use work.proc_package.ALL;

entity proc_controlunit is
	port (
		clk : in std_logic;
		rst : in std_logic;
		en : in std_logic;
		
		-- Instruction
		instruction : in PROC_PROG_DATA_TYPE;
		
		-- Immediate Bus Output
		immediate_value : out PROC_REG_DATA_TYPE;
		
		-- Register File Control
		register_en : out std_logic;
		register_p_0_write : out std_logic;
		register_p_0_write_source : out PROC_MUX_SOURCE;
		register_p_0_addr_direct : out PROC_REG_ADDR_TYPE;
		register_p_1_addr_direct : out PROC_REG_ADDR_TYPE;
		
		-- ALU Control
		alu_en : out std_logic;
		alu_b_source : out PROC_MUX_SOURCE;
		alu_mode : out PROC_ALU_MODE;
		
		-- Program Counter Control
		pc_en : out std_logic;
		pc_jump_source : out PROC_MUX_SOURCE;
		pc_mode : out PROC_PC_MODE;
		
		-- Status Register Control
		sreg_en : out std_logic;
		sreg_source : out PROC_MUX_SOURCE;
		
		-- Status Register Bit Manipulator Control
		sreg_bit_en : out std_logic;
		sreg_bit_index : out PROC_REG_BIT_INDEX_TYPE;
		sreg_bit_value_in : out std_logic;
		sreg_jump_en : out std_logic;
		
		-- Memory Controller Control
		mem_en : out std_logic;
		mem_addr_source : out PROC_MUX_SOURCE
	);
end proc_controlunit;

architecture Behavioral of proc_controlunit is
	--
begin
	-- Implement you control unit here
end Behavioral;

